The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display including a pluraliyt of pixels having a switching element each.
FIG. 1 shows the configuration of a conventional active matrix liquid crystal display device (AM-LCD). This AM-LCD displays images by receiving the signals: a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock, and picture signals. These signals come from a personal computer or the like.
A liquid crystal display panel 1 includes thin film transistors (TFTs) 12 liquid crystal capacitors 13, storage capacitors 14 for improving the quality of displayed images, and gate lines 15, and source lines 16. A gate line 15 is connected to the gate electrodes of the TFTs for supplying a scanning signal to the transistors. A source line 16 is connected to the source electrodes of the TFTs for supplying a signal voltage to the TFTs. The gate lines 15 are connected to a gate driver 2, and the source lines 16 to a source driver 3.
The AM-LCD receives the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the dot clock and the picture signals (display data) synchronized with the dot clock, thereby displaying images on the display panel 1. Specifically, display data corresponding to one horizontal line are stored in the source driver 3 during one horizontal synchronizing period. The stored display data corresponding to one horizontal line are outputted all at once to the source lines of the liquid crystal display panel 1 during the next horizontal synchronizing period. As a scanning signal is inputted to a gate line at the same time, the TFTs on the gate line are turned on and supply electric charges corresponding to the display data to the liquid crystal capacitors. This operation is carryed out for each gate line, and a whole image can be displayed on the display panel.
The functions of the control sections for signals given to the gate driver 2 and the source driver 3 will be described next.
A register 4 holds in advance a value as the counted number of horizontal synchronizing signal pulses corresponding to the period from the switching timing of the vertical synchronizing signal to the starting timing of an effective display data period. A register 5 holds in advance a value as the counted number of dot clock pulses corresponding to the period from the switching timing of the horizontal synchronizing signal to the starting timing of an effective display data period.
A start pulse generation circuit 6 generates a gate start pulse signal and a source start pulse signal for giving start timings to the gate driver 2 and the source driver 3 respectively, on the basis of the signal Vsync, the signal Hsync, the dot clock and the values held in the respective registers 4 and 5. The gate start pulse signal and the source start pulse signal from the start pulse generating circuit 6 determine a display area on the liquid crystal display panel 1.
On the other hand, a start pulse generation circuit 7 generates a gate start pulse signal and a source start pulse signal for giving start timings for the gate driver 2 and the source driver 3 respectively, on the basis of a data enable signal indicating effective display data periods comming from an computer and the signal Vsync. The gate start pulse signal and the source start pulse signal from the start pulse generating circuit 7 determine a display area on the liquid crystal display panel 1. Thus the start pulse generating circuit 7 enables the AM-LCD to control the display area from the outside as far as the horizontal direction is concerned.
The gate start pulse signal generated by the start pulse generation circuits 6 or 7 is inputted to the gate driver 2 through a selector 9, and the source start pulse signal generated by the circuits 6 or 7 is inputted to the source driver 3 through a selector 8. Each of the selectors 8 and 9 selects these start pulse signals in response to a select signal from a computer.
A circuit 10 converts picture signals (display data) into A.C. signals in a specified a frequency (for example, 50 or 60 Hz) and sends them to the source driver 3.
There are two modes for displaying images; one is the display fixing mode, in which the display area is fixed on a specified position, and the other is the display control mode, in which the display area can be controlled signals from the outside. The operations according to these display modes will now be described as follows.
(1) Display Fixing Mode
FIG. 2A shows a timing chart for describing the operation of this mode. Referring to the register 4 holding the value, the start pulse generation circuit 6 counts the pulses of the signal Hsync, with the switching timing of the signal Vsync as a starting point, and generates a gate start pulse signal Vsp1 on the completion of counting up to the value. In other words, the gate start pulse signal Vsp1 is generated after a lapse of a specified length of time Vbp (shown in FIG. 2A) from the switching timing of the signal Vsync.
Besides, referring to the register 5 holding the value, the start pulse generation circuit 6 counts the pulses of the dot clock pulses (not shown) with the switching timing of the signal Hsync as a starting point and generates the source start pulse signal Hsp1 on the completion of counting up to the value. In other words, the source start pulse signal Hsp1 is generated after a lapse of a specified length Hbp (shown in FIG. 2A) from the switching timing of the signal Hsync.
While a select signal that indicates the display fixing mode is being inputted to the selectors from a computer, the signal Vsp1 and the signal Hsp1 that are generated by the start pulse generating circuit 6 are selected by the selectors 8 and 9, and being inputted to the gate driver 2 and the source driver 3.
The source driver 3 starts to output the stored display data A, B, C, D, E, . . . to the source lines in synchronism with the Hsp1 on receiving the signal Vsp1. At the same time, the gate driver 2 starts to output scanning signals G1, G2, G3, G4, . . . sequentially to the gate lines in synchronism with the Hsp1. As a result, a whole image including the display data A, B, C, D, E, . . . can be displayed in a specified position on the liquid crystal display panel 1.
(2) Display Control Mode
A data enable signal indicating effective display data periods keeps an enable level during an effective display data period, and keeps a disable level during an invalid display data period. As shown in FIG. 2B, a source start pulse signal Hsp2 is generated at the timing when the data enable signal goes to the enable level. Besides, a gate start pulse signal Vsp2 is generated at the timing when the data enable signal goes to the enable level after the first pulse of the signal Hsp2.
While the select signal indicating the display control mode is being inputted to the selectors from a computer, the signal Vsp2 and the signal Hsp2 that are generated by the start pulse generating circuit 7 are selected by the selectors 8 and 9 and being inputted to the gate driver 2 and the source driver 3, respectively.
The source driver 3 starts to output the stored display data A, B, C, D, E, . . . to the source lines in synchronism with the signal Hsp2 on receiving the signal Vsp2. At the same time, the gate drives 2 starts to output the scanning signals G1, G2, G3, G4, . . . , sequentially to the gate lines in synchronism with the signal Hsp2. As a result, a whole image including the display data A, B, C, D, E, . . . , can be displayed in a desired position on the liquid crystal display panel 1.
Thus, two interface signals, namely, the data enable signal and the select signal are necessary for the display control mode in addition to the five signals: the signal Vsync, the signal Hsync, and the analog picture signals R, G and B. Therefore, the conventional AM-LCDs require seven signals each. In view of simplifying the interface of the liquid crystal display device, the input number is larger than that of a CRT, which requires five interface signals: the signal Vsync, the signal Hsync, and the analog picture signals R, G, and B. Accordingly, it is a important issue to reduce the number of the interface signals in the AM-LCDs.
It is an object of this invention to provide a liquid crystal display device which can achieve a simple interface.
A liquid crystal display device comprising a selector and a data enable signal detection circuit, the selector having a function of selecting display modes in response to a select signal, and the data enable signal circuit generating the select signal in response to a data enable signal indicating effective display data periods from the outside.
In the above case, the selector may be provided so as to select the first display mode in case the select signal is inactive and select the second display mode in case it is active, and the data enable signal detection circuit generating the select signal set to be inactive when the data enable signal indicating an effective data period is not detected for a specified length of time and the select signal to be active when the data enable signal indicating an effective data period is detected within the period.
Moreover, the data enable signal detection circuit may comprise a D flip-flop which inputs the vertical synchronizing signal concerning the received image from the outside to its clock input terminal, the data enable signal to its data input terminal, holding the signal level of the data enable signal at the rise timing of the vertical synchronizing signal, and outputting the held level.
Furthermore, the data enable signal detection circuit may comprise a one-shot multivibrator which has a circuit including a resistor and a capacitor with a time constant longer than the cycle of the vertical synchronizing signal pulses concerning the received image from the outside, inputting the data enable signal, outputs a signal to be inactive when the data enable signal indicating an effective display data period is not received for a length of time longer than the cycle of the vertical synchronizing signal pulses, and outputs a signal to be inactive signal when the data enable signal indicating an effective display data period is received during the cycle.
According to this invention, the select signal for selecting one of the two modes is generated on the basis of the data enable signal indicating effective display data periods concerning the display data. Consequently, the interface of the AM-LCD can be simplified because the select signal from the outside is unnecessary.